Intel® Quartus® Prime Standard Edition User Guide: Design Recommendations

ID 683323
Date 9/24/2018
Document Table of Contents Specifying a Power-Up Value

Options available in synthesis tools allow you to specify power-up conditions for the design. Intel® Quartus® Prime Standard Edition integrated synthesis provides the Power-Up Level logic option.

You can also specify the power-up level with an altera_attribute assignment in the source code. This attribute forces synthesis to perform NOT gate push-back, because synthesis tools cannot change the power-up states of core registers.

You can apply the Power-Up Level logic option to a specific register, or to a design entity, module, or sub design. When you assign this option, every register in that block receives the value. Registers power up to 0 by default. Therefore, you can use this assignment to force all registers to power-up to 1 using NOT gate push-back.

Setting the Power-Up Level to a logic level of high for a large design entity could degrade the quality of results due to the number of inverters that requires. In some situations, this design style causes issues due to enable signal inference or secondary control logic inference. It may also be more difficult to migrate this type of designs.

Some synthesis tools can also read the default or initial values for registered signals and implement this behavior in the device. For example, Intel® Quartus® Prime Standard Edition integrated synthesis converts default values for registered signals into Power-Up Level settings. When the Intel® Quartus® Prime software reads the default values, the synthesized behavior matches the power-up state of the HDL code during a functional simulation.

Verilog Register with High Power-Up Value

reg q = 1’b1; //q has a default value of ‘1’

always @ (posedge clk)
	q <= d;

VHDL Register with High Power-Up Level

SIGNAL q : STD_LOGIC := '1'; -- q has a default value of '1'

PROCESS (clk, reset)
	IF (rising_edge(clk)) THEN
		q <= d;
Your design may contain undeclared default power-up conditions based on signal type. If you declare a VHDL register signal as an integer, Intel® Quartus® Prime synthesis uses the left end of the integer range as the power-up value. For the default signed integer type, the default power-up value is the highest magnitude negative integer (100…001). For an unsigned integer type, the default power-up value is 0.
Note: If the target device architecture does not support two asynchronous control signals, such as aclr and aload, you cannot set a different power-up state and reset state. If the NOT gate push-back algorithm creates logic to set a register to 1, that register powers-up high. If you set a different power-up condition through a synthesis attribute or initial value, synthesis ignores the power-up level.