Intel® Quartus® Prime Standard Edition User Guide: Design Recommendations

ID 683323
Date 9/24/2018
Document Table of Contents

2.8. Recommended HDL Coding Styles Revision History

The following revisions history applies to this chapter:

Document Version Intel® Quartus® Prime Version Changes
2018.09.24 18.1.0
  • Initial release in Intel Quartus Prime Standard Edition User Guide.
  • Renamed topic: "Use the Device Synchronous Load (sload) Signal to Initialize" to "Initialize the Device with the Synchronous Load (sload) Signal"
2017.05.08 17.0.0
  • Updated example: Verilog HDL Multiply-Accumulator
  • Revised Check Read-During-Write Behavior.
  • Revised Controlling RAM Inference and Implementation.
  • Revised Single-Clock Synchronous RAM with Old Data Read-During-Write Behavior.
  • Revised Single-Clock Synchronous RAM with New Data Read-During-Write Behavior.
  • Updated and moved template for VHDL Single-Clock Simple Dual Port Synchronous RAM with New Data Read-During-Write Behavior.
  • Revised Inferring ROM Functions from HDL Code.
  • Created example: Avoid this VHDL Coding Style.
2016.05.03 16.0.0
  • Updated example code templates with latest coding styles.
2015.11.02 15.1.0
  • Changed instances of Quartus II to Intel® Quartus® Prime .
2015.05.04 15.0.0 Added information and reference about ramstyle attribute for sift register inference.
2014.12.15 14.1.0 Updated location of Fitter Settings, Analysis & Synthesis Settings, and Physical Optimization Settings to Compiler Settings.
2014.08.18 14.0.a10.0
  • Added recommendation to use register pipelining to obtain high performance in DSP designs.
2014.06.30 14.0.0 Removed obsolete MegaWizard Plug-In Manager support.
November 2013 13.1.0 Removed HardCopy device support.
June 2012 12.0.0
  • Revised section on inserting Altera templates.
  • Code update for Example 11-51.
  • Minor corrections and updates.
November 2011 11.1.0
  • Updated document template.
  • Minor updates and corrections.
December 2010 10.1.0
  • Changed to new document template.
  • Updated Unintentional Latch Generation content.
  • Code update for Example 11-18.
July 2010 10.0.0
  • Added support for mixed-width RAM
  • Updated support for no_rw_check for inferring RAM blocks
  • Added support for byte-enable
November 2009 9.1.0
  • Updated support for Controlling Inference and Implementation in Device RAM Blocks
  • Updated support for Shift Registers
March 2009 9.0.0
  • Corrected and updated several examples
  • Added support for Arria II GX devices
  • Other minor changes to chapter
November 2008 8.1.0 Changed to 8-1/2 x 11 page size. No change to content.
May 2008 8.0.0

Updates for the Intel® Quartus® Prime software version 8.0 release, including:

  • Added information to “RAM
  • Functions—Inferring ALTSYNCRAM and ALTDPRAM Megafunctions from HDL Code” on page 6–13
  • Added information to “Avoid Unsupported Reset and Control Conditions” on page 6–14
  • Added information to “Check Read‑During‑Write Behavior” on page 6–16
  • Added two new examples to “ROM Functions—Inferring ALTSYNCRAM and LPM_ROM Megafunctions from HDL Code” on page 6–28: Example 6–24 and Example 6–25
  • Added new section: “Clock Multiplexing” on page 6–46
  • Added hyperlinks to references within the chapter
  • Minor editorial updates