3.1.3. How Timing Constraints Affect Synchronizer Identification and Metastability Analysis
In addition, the Auto and Forced If Asynchronous synchronizer identification options use timing constraints to automatically detect the synchronizer chains in the design. These options check for signal transfers between circuitry in unrelated or asynchronous clock domains, so clock domains must be related correctly with timing constraints.
The timing analyzer views input ports as asynchronous signals unless they are associated correctly with a clock domain. If an input port fans out to registers that are not acting as synchronization registers, apply a set_input_delay constraint to the input port; otherwise, the input register might be reported as a synchronization register. Constraining a synchronous input port with a set_max_delay constraint for a setup (tSU) requirement does not prevent synchronizer identification because the constraint does not associate the input port with a clock domain.
Instead, use the following command to specify an input setup requirement associated with a clock:
set_input_delay -max -clock < clock name> <latch – launch – tsu requirement> <input port name>
Registers that are at the end of false paths are also considered synchronization registers because false paths are not timing-analyzed. Because there are no timing requirements for these paths, the signal may change at any point, which may violate the tSU and tH of the register. Therefore, these registers are identified as synchronization registers. If these registers are not used for synchronization, you can turn off synchronizer identification and analysis. To do so, set Synchronizer Identification to Off for the first synchronization register in these register chains.
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