ID 683323
Date 9/24/2018
Public

## 1.4.1.1. Use Synchronous Resets

The synchronous reset ensures that the circuit is fully synchronous. You can easily time the circuit with the Intel® Quartus® Prime Timing Analyzer.

Because clocks that are synchronous to each other launch and latch the reset signal, the data arrival and data required times are easily determined for proper slack analysis. The synchronous reset is easier to use with cycle-based simulators.

There are two methods by which a reset signal can reach a register; either by being gated in with the data input, or by using an LAB-wide control signal (synclr). If you use the first method, you risk adding an additional gate delay to the circuit to accommodate the reset signal, which causes increased data arrival times and negatively impacts setup slack. The second method relies on dedicated routing in the LAB to each register, but this is slower than an asynchronous reset to the same register.

Figure 14. Synchronous Reset
Figure 15. LAB-Wide Control Signals

Consider two types of synchronous resets when you examine the timing analysis of synchronous resets—externally synchronized resets and internally synchronized resets. Externally synchronized resets are synchronized to the clock domain outside the FPGA, and are not very common. A power-on asynchronous reset is dual-rank synchronized externally to the system clock and then brought into the FPGA. Inside the FPGA, gate this reset with the data input to the registers to implement a synchronous reset.

Figure 16. Externally Synchronized Reset

The following example shows the Verilog HDL equivalent of the schematic. When you use synchronous resets, the reset signal is not put in the sensitivity list.

The following example shows the necessary modifications that you should make to the internally synchronized reset.

### Verilog HDL Code for Externally Synchronized Reset


module sync_reset_ext (
input   clock,
input   reset_n,
input   data_a,
input   data_b,
output  out_a,
output  out_b
);
reg      reg1, reg2
assign   out_a  = reg1;
assign   out_b  = reg2;
always @ (posedge clock)
begin
if (!reset_n)
begin
reg1     <= 1’b0;
reg2     <= 1’b0;
end
else
begin
reg1     <= data_a;
reg2     <= data_b;
end
end
endmodule     //  sync_reset_ext


The following example shows the constraints for the externally synchronous reset. Because the external reset is synchronous, you only need to constrain the reset_n signal as a normal input signal with set_input_delay constraint for -max and -min.

### SDC Constraints for Externally Synchronized Reset


# Input clock - 100 MHz
create_clock [get_ports {clock}] \
-name {clock} \
-period 10.0 \
-waveform {0.0 5.0}
# Input constraints on low-active reset
# and data
set_input_delay 7.0 \
-max \
-clock [get_clocks {clock}] \
[get_ports {reset_n data_a data_b}]
set_input_delay 1.0 \
-min \
-clock [get_clocks {clock}] \
[get_ports {reset_n data_a data_b}]


More often, resets coming into the device are asynchronous, and must be synchronized internally before being sent to the registers.

Figure 17. Internally Synchronized Reset

The following example shows the Verilog HDL equivalent of the schematic. Only the clock edge is in the sensitivity list for a synchronous reset.

### Verilog HDL Code for Internally Synchronized Reset


module sync_reset (
input clock,
input reset_n,
input data_a,
input data_b,
output out_a,
output out_b
);
reg 	reg1, reg2
reg 	reg3, reg4

assign 	out_a = reg1;
assign 	out_b = reg2;
assign 	rst_n = reg4;

always @ (posedge clock)
begin
if (!rst_n)
begin
reg1 <= 1’bo;
reg2 <= 1’b0;
end
else
begin
reg1 <= data_a;
reg2 <= data_b;
end
end

always @ (posedge clock)
begin
reg3 <= reset_n;
reg4 <= reg3;
end
endmodule // sync_reset


The SDC constraints are similar to the external synchronous reset, except that the input reset cannot be constrained because it is asynchronous. Cut the input path with a set_false_path statement to avoid these being considered as unconstrained paths.

### SDC Constraints for Internally Synchronized Reset


# Input clock - 100 MHz
create_clock [get_ports {clock}] \
-name {clock} \
-period 10.0 \
-waveform {0.0 5.0}
# Input constraints on data
set_input_delay 7.0 \
-max \
-clock [get_clocks {clock}] \
[get_ports {data_a data_b}]
set_input_delay 1.0 \
-min \
-clock [get_clocks {clock}] \
[get_ports {data_a data_b}]
# Cut the asynchronous reset input
set_false_path \
-from [get_ports {reset_n}] \
-to [all_registers]


An issue with synchronous resets is their behavior with respect to short pulses (less than a period) on the asynchronous input to the synchronizer flipflops. This can be a disadvantage because the asynchronous reset requires a pulse width of at least one period wide to guarantee that it is captured by the first flipflop. However, this can also be viewed as an advantage in that this circuit increases noise immunity. Spurious pulses on the asynchronous input have a lower chance of being captured by the first flipflop, so the pulses do not trigger a synchronous reset. In some cases, you might want to increase the noise immunity further and reject any asynchronous input reset that is less than n periods wide to debounce an asynchronous input reset.

Figure 18. Internally Synchronized Reset with Pulse Extender

Junction dots indicate the number of stages. You can have more flipflops to get a wider pulse that spans more clock cycles.

Many designs have more than one clock signal. In these cases, use a separate reset synchronization circuit for each clock domain in the design. When you create synchronizers for PLL output clocks, these clock domains are not reset until you lock the PLL and the PLL output clocks are stable. If you use the reset to the PLL, this reset does not have to be synchronous with the input clock of the PLL. You can use an asynchronous reset for this. Using a reset to the PLL further delays the assertion of a synchronous reset to the PLL output clock domains when using internally synchronized resets.