Intel® Quartus® Prime Standard Edition User Guide: Design Recommendations

ID 683323
Date 9/24/2018
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2.4.3.1. Simple Shift Register

The examples in this section show a simple, single-bit wide, 67-bit long shift register.

Intel® Quartus® Prime synthesis implements the register (W = 1 and M = 67) in an ALTSHIFT_TAPS IP core for supported devices and maps it to RAM in supported devices, which may be placed in dedicated RAM blocks or MLAB memory. If the length of the register is less than 67 bits, Intel® Quartus® Prime synthesis implements the shift register in logic.

Verilog HDL Single-Bit Wide, 64-Bit Long Shift Register

module shift_1x67 (clk, shift, sr_in, sr_out);
	input clk, shift;
	input sr_in;
	output sr_out;

	reg [66:0] sr;

	always @ (posedge clk)
	begin
		if (shift == 1'b1)
		begin
			sr[66:1] <= sr[65:0];
			sr[0] <= sr_in;
		end
	end
	assign sr_out = sr[65];
endmodule

VHDL Single-Bit Wide, 64-Bit Long Shift Register

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
ENTITY shift_1x67 IS
	PORT (
		clk: IN STD_LOGIC;
		shift: IN STD_LOGIC;
		sr_in: IN STD_LOGIC;
		sr_out: OUT STD_LOGIC
	);
END shift_1x67;

ARCHITECTURE arch OF shift_1x67 IS
	TYPE sr_length IS ARRAY (66 DOWNTO 0) OF STD_LOGIC;
	SIGNAL sr: sr_length;
BEGIN
	PROCESS (clk)
		BEGIN
		IF (rising_edge(clk)) THEN
			IF (shift = '1') THEN
			sr(66 DOWNTO 1) <= sr(65 DOWNTO 0);
			sr(0) <= sr_in;
			END IF;
		END IF;
	END PROCESS;
	sr_out <= sr(65);
END arch;