Intel® Quartus® Prime Standard Edition User Guide: Design Recommendations

ID 683323
Date 9/24/2018
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2.4.1.2. Avoid Unsupported Reset and Control Conditions

To ensure correct implementation of HDL code in the target device architecture, avoid unsupported reset conditions or other control logic that does not exist in the device architecture.

The RAM contents of Intel FPGA memory blocks cannot be cleared with a reset signal during device operation. If your HDL code describes a RAM with a reset signal for the RAM contents, the logic is implemented in regular logic cells instead of a memory block. Do not place RAM read or write operations in an always block or process block with a reset signal. To specify memory contents, initialize the memory or write the data to the RAM during device operation.

In addition to reset signals, other control logic can prevent synthesis from inferring memory logic as a memory block. For example, if you use a clock enable on the read address registers, you can alter the output latch of the RAM, resulting in the synthesized RAM result not matching the HDL description. Use the address stall feature as a read address clock enable to avoid this limitation. Check the documentation for your FPGA device to ensure that your code matches the hardware available in the device.

Verilog RAM with Reset Signal that Clears RAM Contents: Not Supported in Device Architecture

module clear_ram
(
	input clock, reset, we,
	input [7:0] data_in,
	input [4:0] address,
	output reg [7:0] data_out
);

	reg [7:0] mem [0:31];
	integer i;

	always @ (posedge clock or posedge reset)
	begin
		if (reset == 1'b1)
			mem[address] <= 0;
		else if (we == 1'b1)
			mem[address] <= data_in;

		data_out <= mem[address];
	end
endmodule

Verilog RAM with Reset Signal that Affects RAM: Not Supported in Device Architecture

module bad_reset
(
	input clock,
	input reset,
	input we,
	input [7:0] data_in,
	input [4:0] address,
	output reg [7:0] data_out,
	input d,
	output reg q
);

	reg [7:0] mem [0:31];
	integer i;

	always @ (posedge clock or posedge reset)
	begin
		if (reset == 1'b1)
			q <= 0;
		else
		begin
			if (we == 1'b1)
				mem[address] <= data_in;

			data_out <= mem[address];
			q <= d;
		end
	end
endmodule