2.1. Using Provided HDL Templates 2.2. Instantiating IP Cores in HDL 2.3. Inferring Multipliers and DSP Functions 2.4. Inferring Memory Functions from HDL Code 2.5. Register and Latch Coding Guidelines 2.6. General Coding Guidelines 2.7. Designing with Low-Level Primitives 2.8. Recommended HDL Coding Styles Revision History
188.8.131.52. Use Synchronous Memory Blocks 184.108.40.206. Avoid Unsupported Reset and Control Conditions 220.127.116.11. Check Read-During-Write Behavior 18.104.22.168. Controlling RAM Inference and Implementation 22.214.171.124. Single-Clock Synchronous RAM with Old Data Read-During-Write Behavior 126.96.36.199. Single-Clock Synchronous RAM with New Data Read-During-Write Behavior 188.8.131.52. Simple Dual-Port, Dual-Clock Synchronous RAM 184.108.40.206. True Dual-Port Synchronous RAM 220.127.116.11. Mixed-Width Dual-Port RAM 18.104.22.168. RAM with Byte-Enable Signals 22.214.171.124. Specifying Initial Memory Contents at Power-Up
126.96.36.199. If Performance is Important, Optimize for Speed 188.8.131.52. Use Separate CRC Blocks Instead of Cascaded Stages 184.108.40.206. Use Separate CRC Blocks Instead of Allowing Blocks to Merge 220.127.116.11. Take Advantage of Latency if Available 18.104.22.168. Save Power by Disabling CRC Blocks When Not in Use 22.214.171.124. Initialize the Device with the Synchronous Load (sload) Signal
3.4.1. Apply Complete System-Centric Timing Constraints for the Timing Analyzer 3.4.2. Force the Identification of Synchronization Registers 3.4.3. Set the Synchronizer Data Toggle Rate 3.4.4. Optimize Metastability During Fitting 3.4.5. Increase the Length of Synchronizers to Protect and Optimize 3.4.6. Set Fitter Effort to Standard Fit instead of Auto Fit 3.4.7. Increase the Number of Stages Used in Synchronizers 3.4.8. Select a Faster Speed Grade Device
1.4.4. Avoid Asynchronous Register Control Signals
Avoid using an asynchronous load signal if the design target device architecture does not include registers with dedicated circuitry for asynchronous loads. Also, avoid using both asynchronous clear and preset if the architecture provides only one of these control signals.
Some Intel devices directly support an asynchronous clear function, but not a preset or load function. When the target device does not directly support the signals, the synthesis or placement and routing software must use combinational logic to implement the same functionality. In addition, if you use signals in a priority other than the inherent priority in the device architecture, combinational logic may be required to implement the necessary control signals. Combinational logic is less efficient and can cause glitches and other problems; it is best to avoid these implementations.
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