2.1. Using Provided HDL Templates 2.2. Instantiating IP Cores in HDL 2.3. Inferring Multipliers and DSP Functions 2.4. Inferring Memory Functions from HDL Code 2.5. Register and Latch Coding Guidelines 2.6. General Coding Guidelines 2.7. Designing with Low-Level Primitives 2.8. Recommended HDL Coding Styles Revision History
18.104.22.168. Use Synchronous Memory Blocks 22.214.171.124. Avoid Unsupported Reset and Control Conditions 126.96.36.199. Check Read-During-Write Behavior 188.8.131.52. Controlling RAM Inference and Implementation 184.108.40.206. Single-Clock Synchronous RAM with Old Data Read-During-Write Behavior 220.127.116.11. Single-Clock Synchronous RAM with New Data Read-During-Write Behavior 18.104.22.168. Simple Dual-Port, Dual-Clock Synchronous RAM 22.214.171.124. True Dual-Port Synchronous RAM 126.96.36.199. Mixed-Width Dual-Port RAM 188.8.131.52. RAM with Byte-Enable Signals 184.108.40.206. Specifying Initial Memory Contents at Power-Up
220.127.116.11. If Performance is Important, Optimize for Speed 18.104.22.168. Use Separate CRC Blocks Instead of Cascaded Stages 22.214.171.124. Use Separate CRC Blocks Instead of Allowing Blocks to Merge 126.96.36.199. Take Advantage of Latency if Available 188.8.131.52. Save Power by Disabling CRC Blocks When Not in Use 184.108.40.206. Initialize the Device with the Synchronous Load (sload) Signal
3.4.1. Apply Complete System-Centric Timing Constraints for the Timing Analyzer 3.4.2. Force the Identification of Synchronization Registers 3.4.3. Set the Synchronizer Data Toggle Rate 3.4.4. Optimize Metastability During Fitting 3.4.5. Increase the Length of Synchronizers to Protect and Optimize 3.4.6. Set Fitter Effort to Standard Fit instead of Auto Fit 3.4.7. Increase the Number of Stages Used in Synchronizers 3.4.8. Select a Faster Speed Grade Device
220.127.116.11. Verilog HDL State Machines
To ensure proper recognition and inference of Verilog HDL state machines, observe the following additional Verilog HDL guidelines.
Refer to your synthesis tool documentation for specific coding recommendations. If the synthesis tool doesn't recognize and infer the state machine, the tool implements the state machine as regular logic gates and registers, and the state machine doesn't appear as a state machine in the Analysis & Synthesis section of the Intel® Quartus® Prime Compilation Report. In this case, Intel® Quartus® Prime synthesis does not perform any optimizations specific to state machines.
- If you are using the SystemVerilog standard, use enumerated types to describe state machines.
- Represent the states in a state machine with the parameter data types in Verilog-1995 and Verilog-2001, and use the parameters to make state assignments. This parameter implementation makes the state machine easier to read and reduces the risk of errors during coding.
- Do not directly use integer values for state variables, such as next_state <= 0. However, using an integer does not prevent inference in the Intel® Quartus® Prime software.
- Intel® Quartus® Prime software doesn't infer a state machine if the state transition logic uses arithmetic similar to the following example:
case (state) 0: begin if (ena) next_state <= state + 2; else next_state <= state + 1; end 1: begin ... endcase
- Intel® Quartus® Prime software doesn't infer a state machine if the state variable is an output.
- Intel® Quartus® Prime software doesn't infer a state machine for signed variables.
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