Intel® Quartus® Prime Standard Edition User Guide: Design Recommendations

ID 683323
Date 9/24/2018
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3.4.1. Apply Complete System-Centric Timing Constraints for the Timing Analyzer

To enable the Intel® Quartus® Prime metastability features, make sure that the timing analyzer is used for timing analysis.

Ensure that the design is fully timing constrained and that it meets its timing requirements. If the synchronization chain does not meet its timing requirements, MTBF cannot be calculated. If the clock domain constraints are set up incorrectly, the signal transfers between circuitry in unrelated or asynchronous clock domains might be identified incorrectly.

Use industry-standard system-centric I/O timing constraints instead of using FPGA-centric timing constraints.

You should use set_input_delay constraints in place of set_max_delay constraints to associate each input port with a clock domain to help eliminate false positives during synchronization register identification.