2.1. Using Provided HDL Templates 2.2. Instantiating IP Cores in HDL 2.3. Inferring Multipliers and DSP Functions 2.4. Inferring Memory Functions from HDL Code 2.5. Register and Latch Coding Guidelines 2.6. General Coding Guidelines 2.7. Designing with Low-Level Primitives 2.8. Recommended HDL Coding Styles Revision History
22.214.171.124. Use Synchronous Memory Blocks 126.96.36.199. Avoid Unsupported Reset and Control Conditions 188.8.131.52. Check Read-During-Write Behavior 184.108.40.206. Controlling RAM Inference and Implementation 220.127.116.11. Single-Clock Synchronous RAM with Old Data Read-During-Write Behavior 18.104.22.168. Single-Clock Synchronous RAM with New Data Read-During-Write Behavior 22.214.171.124. Simple Dual-Port, Dual-Clock Synchronous RAM 126.96.36.199. True Dual-Port Synchronous RAM 188.8.131.52. Mixed-Width Dual-Port RAM 184.108.40.206. RAM with Byte-Enable Signals 220.127.116.11. Specifying Initial Memory Contents at Power-Up
18.104.22.168. If Performance is Important, Optimize for Speed 22.214.171.124. Use Separate CRC Blocks Instead of Cascaded Stages 126.96.36.199. Use Separate CRC Blocks Instead of Allowing Blocks to Merge 188.8.131.52. Take Advantage of Latency if Available 184.108.40.206. Save Power by Disabling CRC Blocks When Not in Use 220.127.116.11. Initialize the Device with the Synchronous Load (sload) Signal
3.4.1. Apply Complete System-Centric Timing Constraints for the Timing Analyzer 3.4.2. Force the Identification of Synchronization Registers 3.4.3. Set the Synchronizer Data Toggle Rate 3.4.4. Optimize Metastability During Fitting 3.4.5. Increase the Length of Synchronizers to Protect and Optimize 3.4.6. Set Fitter Effort to Standard Fit instead of Auto Fit 3.4.7. Increase the Number of Stages Used in Synchronizers 3.4.8. Select a Faster Speed Grade Device
18.104.22.168. Avoid Delay Chains in Clock Paths
Delays in PLD designs can change with each placement and routing cycle. Effects such as rise and fall time differences and on-chip variation mean that delay chains, especially those placed on clock paths, can cause significant problems in your design. Avoid using delay chains to prevent these kinds of problems.
You require delay chains when you use two or more consecutive nodes with a single fan-in and a single fan-out to cause delay. Inverters are often chained together to add delay. Delay chains are sometimes used to resolve race conditions created by other asynchronous design practices.
In some ASIC designs, delays are used for buffering signals as they are routed around the device. This functionality is not required in FPGA devices because the routing structure provides buffers throughout the device.
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