Intel® Quartus® Prime Standard Edition User Guide: Design Recommendations

ID 683323
Date 9/24/2018
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2.5.2. Secondary Register Control Signals Such as Clear and Clock Enable

The registers in Intel FPGAs provide a number of secondary control signals. Use these signals to implement control logic for each register without using extra logic cells. Intel FPGA device families vary in their support for secondary signals, so consult the device family data sheet to verify which signals are available in your target device.

To make the most efficient use of the signals in the device, ensure that HDL code matches the device architecture as closely as possible. The control signals have a certain priority due to the nature of the architecture. Your HDL code must follow that priority where possible.

Your synthesis tool can emulate any control signals using regular logic, so achieving functionally correct results is always possible. However, if your design requirements allow flexibility in controlling use and priority of control signals, match your design to the target device architecture to achieve the most efficient results. If the priority of the signals in your design is not the same as that of the target architecture, you may require extra logic to implement the control signals. This extra logic uses additional device resources, and can cause additional delays for the control signals.

In certain cases, using logic other than the dedicated control logic in the device architecture can have a larger impact. For example, the clock enable signal has priority over the synchronous reset or clear signal in the device architecture. The clock enable turns off the clock line in the LAB, and the clear signal is synchronous. Therefore, in the device architecture, the synchronous clear takes effect only when a clock edge occurs.

If you define a register with a synchronous clear signal that has priority over the clock enable signal, Intel® Quartus® Prime synthesis emulates the clock enable functionality using data inputs to the registers. You cannot apply a Clock Enable Multicycle constraint, because the emulated functionality does not use the clock enable port of the register. In this case, using a different priority causes unexpected results with an assignment to the clock enable signal.

The signal order is the same for all Intel FPGA device families. However, not all device families provide every signal. The priority order is:

  1. Asynchronous Clear (aclr )—highest priority
  2. Asynchronous Load (aload)—not available on Intel® Arria® 10 devices
  3. Enable (ena)
  4. Synchronous Clear (sclr)
  5. Synchronous Load (sload)
  6. Data In (data)—lowest priority

The priority order for secondary control signals in Intel FPGA devices differs from the order for other vendors’ FPGA devices. If your design requirements are flexible regarding priority, verify that the secondary control signals meet design performance requirements when migrating designs between FPGA vendors. To achieve the best results. try to match your target device architecture.

The following Verilog HDL and VHDL examples create a register with the aclr, aload, and ena control signals.

Verilog HDL D-Type Flipflop (Register) With ena, aclr, and aload Control Signals

This example does not have adata on the sensitivity list. This is a limitation of the Verilog HDL language—there is no way to describe an asynchronous load signal (in which q toggles if adata toggles while aload is high). Despite this limitation, many synthesis tools infer an aload signal from this construct. When they perform such inference, you may see information or warning messages from the synthesis tool.

module dff_control(clk, aclr, aload, ena, data, adata, q);
    input clk, aclr, aload, ena, data, adata;
    output q;

    reg q;

    always @ (posedge clk or posedge aclr or posedge aload)
    begin
        if (aclr)
            q <= 1'b0;
        else if (aload)
            q <= adata;
        else if (ena)
            q <= data;
    end
endmodule

VHDL D-Type Flipflop (Register) With ena, aclr, and aload Control Signals

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY dff_control IS
	PORT (
		clk: IN STD_LOGIC;
		aclr: IN STD_LOGIC;
		aload: IN STD_LOGIC;
		adata: IN STD_LOGIC;
		ena: IN STD_LOGIC;
	  data: IN STD_LOGIC;
q: OUT STD_LOGIC
	);
END dff_control;
ARCHITECTURE rtl OF dff_control IS
BEGIN
	PROCESS (clk, aclr, aload, adata)
	BEGIN
IF (aclr = '1') THEN
q <= '0';
ELSIF (aload = '1') THEN
q <= adata;
ELSE
			IF (rising_edge(clk)) THEN
				IF (ena	 ='1') THEN
q <= data;
				END IF;
			END IF;
		END IF;
	END PROCESS;
END rtl;