Intel® Quartus® Prime Standard Edition User Guide: Design Recommendations

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ID 683323
Date 9/24/2018
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Document Table of Contents
Document Table of Contents x
1. Recommended Design Practices 2. Recommended HDL Coding Styles 3. Managing Metastability with the Intel® Quartus® Prime Software A. Intel® Quartus® Prime Standard Edition User Guides
1. Recommended Design Practices x
1.1. Following Synchronous FPGA Design Practices 1.2. HDL Design Guidelines 1.3. Checking Design Violations 1.4. Use Clock and Register-Control Architectural Features 1.5. Implementing Embedded RAM 1.6. Recommended Design Practices Revision History
1.1. Following Synchronous FPGA Design Practices x
1.1.1. Implementing Synchronous Designs 1.1.2. Asynchronous Design Hazards
1.2. HDL Design Guidelines x
1.2.1. Optimizing Combinational Logic 1.2.2. Optimizing Clocking Schemes 1.2.3. Optimizing Physical Implementation and Timing Closure 1.2.4. Optimizing Power Consumption 1.2.5. Managing Design Metastability
1.2.1. Optimizing Combinational Logic x
1.2.1.1. Avoid Combinational Loops 1.2.1.2. Avoid Unintended Latch Inference 1.2.1.3. Avoid Delay Chains in Clock Paths 1.2.1.4. Use Synchronous Pulse Generators
1.2.2. Optimizing Clocking Schemes x
1.2.2.1. Register Combinational Logic Outputs 1.2.2.2. Avoid Asynchronous Clock Division 1.2.2.3. Avoid Ripple Counters 1.2.2.4. Use Multiplexed Clocks 1.2.2.5. Use Gated Clocks 1.2.2.6. Use Synchronous Clock Enables
1.2.2.5. Use Gated Clocks x
1.2.2.5.1. Recommended Clock-Gating Methods
1.2.3. Optimizing Physical Implementation and Timing Closure x
1.2.3.1. Planning Physical Implementation 1.2.3.2. Planning FPGA Resources 1.2.3.3. Optimizing for Timing Closure 1.2.3.4. Optimizing Critical Timing Paths
1.3. Checking Design Violations x
1.3.1. Validating Against Design Rules 1.3.2. Creating Custom Design Rules
1.3.2. Creating Custom Design Rules x
1.3.2.1. Custom Design Rule Examples
1.4. Use Clock and Register-Control Architectural Features x
1.4.1. Use Global Reset Resources 1.4.2. Use Global Clock Network Resources 1.4.3. Use Clock Region Assignments to Optimize Clock Constraints 1.4.4. Avoid Asynchronous Register Control Signals
1.4.1. Use Global Reset Resources x
1.4.1.1. Use Synchronous Resets 1.4.1.2. Using Asynchronous Resets 1.4.1.3. Use Synchronized Asynchronous Reset
1.4.3. Use Clock Region Assignments to Optimize Clock Constraints x
1.4.3.1. Clock Region Assignments in Intel® Arria® 10 and Older Device Families
2. Recommended HDL Coding Styles x
2.1. Using Provided HDL Templates 2.2. Instantiating IP Cores in HDL 2.3. Inferring Multipliers and DSP Functions 2.4. Inferring Memory Functions from HDL Code 2.5. Register and Latch Coding Guidelines 2.6. General Coding Guidelines 2.7. Designing with Low-Level Primitives 2.8. Recommended HDL Coding Styles Revision History
2.1. Using Provided HDL Templates x
2.1.1. Inserting HDL Code from a Provided Template
2.3. Inferring Multipliers and DSP Functions x
2.3.1. Inferring Multipliers 2.3.2. Inferring Multiply-Accumulator and Multiply-Adder Functions
2.4. Inferring Memory Functions from HDL Code x
2.4.1. Inferring RAM functions from HDL Code 2.4.2. Inferring ROM Functions from HDL Code 2.4.3. Inferring Shift Registers in HDL Code
2.4.1. Inferring RAM functions from HDL Code x
2.4.1.1. Use Synchronous Memory Blocks 2.4.1.2. Avoid Unsupported Reset and Control Conditions 2.4.1.3. Check Read-During-Write Behavior 2.4.1.4. Controlling RAM Inference and Implementation 2.4.1.5. Single-Clock Synchronous RAM with Old Data Read-During-Write Behavior 2.4.1.6. Single-Clock Synchronous RAM with New Data Read-During-Write Behavior 2.4.1.7. Simple Dual-Port, Dual-Clock Synchronous RAM 2.4.1.8. True Dual-Port Synchronous RAM 2.4.1.9. Mixed-Width Dual-Port RAM 2.4.1.10. RAM with Byte-Enable Signals 2.4.1.11. Specifying Initial Memory Contents at Power-Up
2.4.3. Inferring Shift Registers in HDL Code x
2.4.3.1. Simple Shift Register 2.4.3.2. Shift Register with Evenly Spaced Taps
2.5. Register and Latch Coding Guidelines x
2.5.1. Register Power-Up Values 2.5.2. Secondary Register Control Signals Such as Clear and Clock Enable Verilog HDL D-Type Flipflop (Register) With ena, aclr, and aload Control Signals VHDL D-Type Flipflop (Register) With ena, aclr, and aload Control Signals 2.5.3. Latches
2.5.1. Register Power-Up Values x
2.5.1.1. Specifying a Power-Up Value
2.5.3. Latches x
2.5.3.1. Avoid Unintentional Latch Generation 2.5.3.2. Inferring Latches Correctly
2.6. General Coding Guidelines x
2.6.1. Tri-State Signals 2.6.2. Clock Multiplexing 2.6.3. Adder Trees 2.6.4. State Machine HDL Guidelines 2.6.5. Multiplexer HDL Guidelines 2.6.6. Cyclic Redundancy Check Functions 2.6.7. Comparator HDL Guidelines 2.6.8. Counter HDL Guidelines
2.6.3. Adder Trees x
2.6.3.1. Architectures with 4-Input LUTs in Logic Elements 2.6.3.2. Architectures with 6-Input LUTs in Adaptive Logic Modules
2.6.4. State Machine HDL Guidelines x
2.6.4.1. Verilog HDL State Machines 2.6.4.2. VHDL State Machines
2.6.4.1. Verilog HDL State Machines x
2.6.4.1.1. Verilog-2001 State Machine Coding Example 2.6.4.1.2. SystemVerilog State Machine Coding Example
2.6.4.2. VHDL State Machines x
2.6.4.2.1. VHDL State Machine Coding Example
2.6.5. Multiplexer HDL Guidelines x
2.6.5.1. Intel® Quartus® Prime Software Option for Multiplexer Restructuring 2.6.5.2. Multiplexer Types 2.6.5.3. Implicit Defaults in IF Statements 2.6.5.4. default or OTHERS CASE Assignment
2.6.5.2. Multiplexer Types x
2.6.5.2.1. Binary Multiplexers 2.6.5.2.2. Selector Multiplexers 2.6.5.2.3. Priority Multiplexers
2.6.6. Cyclic Redundancy Check Functions x
2.6.6.1. If Performance is Important, Optimize for Speed 2.6.6.2. Use Separate CRC Blocks Instead of Cascaded Stages 2.6.6.3. Use Separate CRC Blocks Instead of Allowing Blocks to Merge 2.6.6.4. Take Advantage of Latency if Available 2.6.6.5. Save Power by Disabling CRC Blocks When Not in Use 2.6.6.6. Initialize the Device with the Synchronous Load (sload) Signal
3. Managing Metastability with the Intel® Quartus® Prime Software x
3.1. Metastability Analysis in the Intel® Quartus® Prime Software 3.2. Metastability and MTBF Reporting 3.3. MTBF Optimization 3.4. Reducing Metastability Effects 3.5. Scripting Support 3.6. Managing Metastability 3.7. Managing Metastability with the Intel® Quartus® Prime Software Revision History
3.1. Metastability Analysis in the Intel® Quartus® Prime Software x
3.1.1. Synchronization Register Chains 3.1.2. Identify Synchronizers for Metastability Analysis 3.1.3. How Timing Constraints Affect Synchronizer Identification and Metastability Analysis
3.2. Metastability and MTBF Reporting x
3.2.1. Metastability Reports 3.2.2. Synchronizer Data Toggle Rate in MTBF Calculation
3.2.1. Metastability Reports x
3.2.1.1. MTBF Summary Report 3.2.1.2. Synchronizer Summary Report 3.2.1.3. Synchronizer Chain Statistics Report in the Timing Analyzer
3.2.1.1. MTBF Summary Report x
3.2.1.1.1. Typical and Worst-Case MTBF of Design 3.2.1.1.2. Synchronizer Chains 3.2.1.1.3. Increasing Available Settling Time
3.3. MTBF Optimization x
3.3.1. Synchronization Register Chain Length
3.4. Reducing Metastability Effects x
3.4.1. Apply Complete System-Centric Timing Constraints for the Timing Analyzer 3.4.2. Force the Identification of Synchronization Registers 3.4.3. Set the Synchronizer Data Toggle Rate 3.4.4. Optimize Metastability During Fitting 3.4.5. Increase the Length of Synchronizers to Protect and Optimize 3.4.6. Set Fitter Effort to Standard Fit instead of Auto Fit 3.4.7. Increase the Number of Stages Used in Synchronizers 3.4.8. Select a Faster Speed Grade Device
3.5. Scripting Support x
3.5.1. Identifying Synchronizers for Metastability Analysis 3.5.2. Synchronizer Data Toggle Rate in MTBF Calculation 3.5.3. report_metastability and Tcl Command 3.5.4. MTBF Optimization 3.5.5. Synchronization Register Chain Length
1. Recommended Design Practices
2. Recommended HDL Coding Styles
3. Managing Metastability with the Intel® Quartus® Prime Software
A. Intel® Quartus® Prime Standard Edition User Guides

2.5.2. Secondary Register Control Signals Such as Clear and Clock Enable

The registers in Intel FPGAs provide a number of secondary control signals. Use these signals to implement control logic for each register without using extra logic cells. Intel FPGA device families vary in their support for secondary signals, so consult the device family data sheet to verify which signals are available in your target device.

To make the most efficient use of the signals in the device, ensure that HDL code matches the device architecture as closely as possible. The control signals have a certain priority due to the nature of the architecture. Your HDL code must follow that priority where possible.

Your synthesis tool can emulate any control signals using regular logic, so achieving functionally correct results is always possible. However, if your design requirements allow flexibility in controlling use and priority of control signals, match your design to the target device architecture to achieve the most efficient results. If the priority of the signals in your design is not the same as that of the target architecture, you may require extra logic to implement the control signals. This extra logic uses additional device resources, and can cause additional delays for the control signals.

In certain cases, using logic other than the dedicated control logic in the device architecture can have a larger impact. For example, the clock enable signal has priority over the synchronous reset or clear signal in the device architecture. The clock enable turns off the clock line in the LAB, and the clear signal is synchronous. Therefore, in the device architecture, the synchronous clear takes effect only when a clock edge occurs.

If you define a register with a synchronous clear signal that has priority over the clock enable signal, Intel® Quartus® Prime synthesis emulates the clock enable functionality using data inputs to the registers. You cannot apply a Clock Enable Multicycle constraint, because the emulated functionality does not use the clock enable port of the register. In this case, using a different priority causes unexpected results with an assignment to the clock enable signal.

The signal order is the same for all Intel FPGA device families. However, not all device families provide every signal. The priority order is:

  1. Asynchronous Clear (aclr )—highest priority
  2. Asynchronous Load (aload)—not available on Intel® Arria® 10 devices
  3. Enable (ena)
  4. Synchronous Clear (sclr)
  5. Synchronous Load (sload)
  6. Data In (data)—lowest priority

The priority order for secondary control signals in Intel FPGA devices differs from the order for other vendors’ FPGA devices. If your design requirements are flexible regarding priority, verify that the secondary control signals meet design performance requirements when migrating designs between FPGA vendors. To achieve the best results. try to match your target device architecture.

The following Verilog HDL and VHDL examples create a register with the aclr, aload, and ena control signals.

Verilog HDL D-Type Flipflop (Register) With ena, aclr, and aload Control Signals

This example does not have adata on the sensitivity list. This is a limitation of the Verilog HDL language—there is no way to describe an asynchronous load signal (in which q toggles if adata toggles while aload is high). Despite this limitation, many synthesis tools infer an aload signal from this construct. When they perform such inference, you may see information or warning messages from the synthesis tool. 

module dff_control(clk, aclr, aload, ena, data, adata, q);
    input clk, aclr, aload, ena, data, adata;
    output q;

    reg q;

    always @ (posedge clk or posedge aclr or posedge aload)
    begin
        if (aclr)
            q <= 1'b0;
        else if (aload)
            q <= adata;
        else if (ena)
            q <= data;
    end
endmodule

VHDL D-Type Flipflop (Register) With ena, aclr, and aload Control Signals 

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY dff_control IS
	PORT (
		clk: IN STD_LOGIC;
		aclr: IN STD_LOGIC;
		aload: IN STD_LOGIC;
		adata: IN STD_LOGIC;
		ena: IN STD_LOGIC;
	  data: IN STD_LOGIC;
q: OUT STD_LOGIC
	);
END dff_control;
ARCHITECTURE rtl OF dff_control IS
BEGIN
	PROCESS (clk, aclr, aload, adata)
	BEGIN
IF (aclr = '1') THEN
q <= '0';
ELSIF (aload = '1') THEN
q <= adata;
ELSE
			IF (rising_edge(clk)) THEN
				IF (ena	 ='1') THEN
q <= data;
				END IF;
			END IF;
		END IF;
	END PROCESS;
END rtl;
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