Intel® Arria® 10 SoC Development Kit User Guide

ID 683227
Date 7/12/2023
Document Table of Contents
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5.4.5. FPGA Programming over External USB-Blaster

The JTAG chain header provides another method for configuring the FPGA using an external USB-Blaster device with the Quartus Prime Programmer running on a PC. To prevent contention between the JTAG masters, the on-board USB-Blaster is automatically disabled when you connect an external USB-Blaster to the JTAG chain through the JTAG chain header.