F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 10/04/2022
Document Table of Contents

3.2.3. Transaction Layer

Figure 10. Transaction Layer
The Transaction Layer includes the following blocks:
  • Reliability, Availability, and Serviceability (RAS) block: It includes a set of features to maintain the integrity of the link.
    • Transaction Layer inserts an optional ECRC in the transmit logic and checks it in the receive logic to provide End-to-End data protection.
    • When application logic sets TLP Digest (TD) bit in the header of TX TLP, ECRC appends automatically. ECRC generation and checking are not applicable to TLP Bypass Mode.
  • TX block: It sends out TX TLPs that it received from application as it is. It also sends the information about non-posted TLPs to the CPL timeout block for CPL timeout detection.
  • RX block: It consists of the following 2 blocks.
    • Filtering block: This module checks if the TLP is good or bad. It generates the associated error message and completion. It also tracks received completions and updates the completion timeout block.
    • RX Buffer Queue: Separate queues for posted, non-posted and completion transactions. This avoids head-of-queue blocking on the received TLPs and provides flexibility to extract TLPs according to the PCIe ordering rules.
  • Config block: It hosts PCIe Configuration Registers (defined in PCIe Spec) and other proprietary registers outside of PCIe space.
Figure 11. RX Blocks

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