F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 10/04/2022
Public
Document Table of Contents

A.1.3. PCI Express Capability Structures

The layouts of the most basic Capability Structures are provided below. Refer to the PCI Express Base Specification for more information about these registers.

Figure 87. Power Management Capability Structure - Byte Address Offsets and Layout
Figure 88. MSI Capability Structure
Figure 89. PCI Express Capability Structure - Byte Address Offsets and LayoutIn the following table showing the PCI Express Capability Structure, registers that are not applicable to a device are reserved.
Figure 90. MSI-X Capability Structure
Figure 91. PCI Express AER Extended Capability Structure

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