F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 10/04/2022
Public
Document Table of Contents

A.2.2. PCIe Configuration Registers for Each Virtual Function

This section provides a description of the individual registers in the configuration space of each virtual function (VF). To access the configuration space of VFs, refer to the section Address Map for the User Avalon-MM Interface.

Table 128.  PCIe Configuration Registers for Each Virtual Function
Address Range Register Description
0x0 : 0x3C VF PCI-Compatible Configuration Space Header Type0
0x70 : 0xA0 VF PCI Express* Capability Structure
0xB0 : 0xB8 VF MSI-X Capability Structure
0x100 : 0x104 VF Alternative Routing ID (ARI) Capability Structure
0x110 : 0x11C VF TLP Processing Hints Capability Structure
0x19C : 0x1A0 VF Address Translation Services Capability Structure
0x200 : 0x208 VF Access Control Services (ACS) Capability Structure

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