The F-Tile Avalon Streaming Interface for PCI Express supports the option to reset all the PCI Express cores simultaneously or to reset each PCI Express core individually. There is only one PERST# (pin_perst_n) pin on F-Tile which is used for power-on-reset or warm reset. By default, toggling pin_perst_n affects all the PCIE cores in the F-Tile, hence if the F-Tile is bifurcated into two x8 Endpoints, toggling pin_perst_n affects both x8 Endpoints. To reset each port individually, use the GPIO Perst through the GPIO pin (i_gpio_perst#_n) for each port. The FPGA needs to enter user mode before the i_gpio_perst#_n can be active. The ports also require dedicated reference clocks to achieve independence from other ports. In-band reset mechanism such as Hot Reset and the Function-Level Reset (FLR) are alternative methods to reset each port individually.
Each port can be configured to be reset by either pin_perst_n or i_gpio_perst#_n, but not both. Select the Enable Independent Perst option in the IP GUI to enable i_gpio_perst#_n for all the ports. When Enable Independent Perst is de-selected, pin_perst_n is applied to all the ports. When Enable CVP (Intel VSEC) option is selected, GPIO PERST on Port 0 is not supported. The table below shows the reset options for the 2 x8 and 4 x4 bifurcated modes. Port that is mapped to pin_perst links up prior to user mode.
|Bifurcation Mode||Enable Independent Perst||Enable CVP [Intel VSEC]||Port 0||Port 1||Port 2||Port 3|
- pin_perst_n is a "power good" indicator from the associated power domain (to which F-Tile is connected). When Independent Perst is not enabled, it shall qualify that the reference clocks driving the refclk0 - refclk3 ports are stable. If one of the reference clocks becomes stable later, deassert pin_perst_n after this reference clock becomes stable.
- pin_perst_n assertion is required for proper Autonomous F-Tile functionality. In Autonomous mode, F-Tile can successfully link up upon the release of pin_perst_n regardless of the FPGA fabric configuration and sends out Configuration Retry Status (CRS) until the FPGA fabric is configured and ready.
- Avoid trigger pin_perst_n or i_gpio_perst#_n during a Functional Level Reset or before a Functional Level Reset completion. Warm reset or pin_perst_n is allowed 280 µs upon the de-assertion of p#_flr_rcvd_pf_o across all PFs when Functional Level Reset has been fully acknowledged or completed. Otherwise, the F-Tile PCIe IP configuration may not be reloaded correctly and can cause unexpected behaviour. It is not recoverable until the next warm reset is initiated.
- The minimum interval requirement between two back-to-back PERST# or GPIO Perst is 500 µs. The minimum interval time required between the deassertion of the PERST# or GPIO Perst to the assertion of the next PERST# or GPIO Perst is 500 µs.
- The reference clock that is used together with pin_perst_n or i_gpio_perst#_n must be stable before pin_perst_n or i_gpio_perst#_n is deactivated.
- Debug Toolkit access, PHY reconfiguration interface and Hard IP reconfiguration interface read or write is not allowed when the GPIO perst is activated.
- When independent Perst is enabled, clock must be supplied to p0_hip_reconfig_clk port.
- When independent Perst is enabled, you must set bit number 20 of the p0_hip_reconfig_address to 0 when accessing registers through p0_hip_reconfig_* interface. This is applicable when your design requires access to the Hard IP reconfiguration interface for x16 core (p0_hip_reconfig_*).
The following is an example where a single PERST# (pin_perst_n) is driven with independent refclk0 and refclk1. In this example, the add-in card (FPGA and SoC) is powered up first. refclk0 input is fed by the on-board free-running oscillator. refclk1 input driven by the Host becomes stable later. Hence, the PERST# is connected to the Host.
The following is an example of independent GPIO Perst and reference clocks for each port. For the instance where the add-in card (FPGA and SoC) is powered up first, it is not gated by the Perst from the Host System.
Hot Reset is supported as per Hot Reset Section decribed in PCIe Base Specification.
For more information on independent reset, refer to Appendix E : Bifurcated Endpoint Support for Independent Resets of this user guide.
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