F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 10/04/2022
Document Table of Contents

5.10. Power Management Interface

Table 72.  Power Management Interface Signals
Signal Name Direction EP/RP/BP Clock Domain Description
p#_pm_state_o[2:0] Output EP/RP/BP coreclkout_hip /Async

Indicates the current power state.

  • 000b : L0 or IDLE
  • 001b : L0s
  • 010b : L1
  • 011b : L2
  • 100b : L3
Note: For 1 x4 Configuration or Topology H, this output will be async to user clock. It’s recommended to user to sample this output bus a few times to obtain valid value.
p#_pm_dstate_o[c*4-1:0] Output EP/RP/BP Async
Power management D-state for each function.
  • 0001b : D0
  • 1000b : D3
  • Others : uninitialized or invalid
Note: This output is async to user clock. It’s recommended to user to sample this output bus a few times to obtain valid value. There may be invalid cycles in between the transition of two valid states.

Each PF uses four consecutive bits. For example, pm_dstate_o[3:0] corresponds to PF0, pm_dstate_o[7:4] corresponds to PF1, and so on.

For 1 x4 Configuration or Topology H, only lower 16 bits are valid.

p#_apps_pm_xmt_pme_i[7:0] Input EP/BP coreclkout_hip
Note: Not available for p2 and p3.

The application logic asserts this signal for one cycle to wake up the Power Management Capability (PMC) state machine from a D1, D2, or D3 power state. Upon wake-up, the IP core sends a PM_PME message.

For example,apps_pm_xmt_pme_i[0] is for PF0,apps_pm_xmt_pme_i[1] is for PF1, and so on.

For 1 x4 Configuration or Topology H, only lower 4 bits are valid.

p#_app_init_rst_i Input RP coreclkout_hip

The Application Layer uses this signal to request a hot reset to downstream devices. The hot reset request will be sent when a single-cycle pulse is applied to this pin.

p#_surprise_down_err_o Output EP/RP/BP Async

Indicates that a surprise down event is occurring in the controller.

p#_app_req_retry_en_i[x:0] Input EP Async

Note:x=7 for port0 and port 1.

When asserted, PCIe Controller will respond to Configuration TLPs with a CRS (Config Retry Status) if it has not already responded to a Configuration TLP with non-CRS status since the last reset. You can use this to hold off on enumeration. p0_app_req_retry_en_i signal must be tied tie to zero when enabling CvP. For port 2 and port 3 which supported RP mode only, this input will not be used.

For 1 x4 Configuration or Topology H, only lower 4 bits are valid.

Each bit corresponds to a PF. For example, app_req_retry_en_i[0] is for PF0, app_req_retry_en_i[1] is for PF1, and so on.

p#_sys_aux_pwr_det_i Input EP/BP coreclkout_hip

Auxiliary Power Detected. Used to report to the host software that auxiliary power (Vaux) is present. Refer to the Device Status Register in the PCI Express Capability Structure.

Assertion of this signal will put the device into L2 link state instead of L3 link state after L23 Ready state. Tie this signal to “0” when not used.

p#_app_ready_entr_l23_i Input EP/BP coreclkout_hip

The application logic asserts this signal to indicate that it is ready to enter the L2/L3 Ready state. T

he app_ready_entr_l23_i signal is provided for applications that must control the L2/L3 Ready entry (in case certain tasks must be performed before going into L2/L3 Ready).

The core delays sending PM_Enter_L23 (in response to PM_Turn_Off) until this signal becomes active.

It must be kept asserted until L2 entry has completed.

This is a level-sensitive signal.

p#_apps_pm_xmt_turnoff_i Input RP coreclkout_hip

This signal is a request from the Application Layer to generate a PM_Turn_Off message.

The Application Layer must assert this signal for one clock cycle.

The IP core does not return an acknowledgement or grant signal.

The Application Layer must not pulse the same signal again until the previous message has been transmitted.

p#_app_xfer_pending_i Input EP/BP coreclkout_hip

This signal is only valid during L1 state, it is only used to bring device to exit L1 and back to L0 when asserted. It cannot prevent device to enter L1. PowerState field of Power Management Control and Status Register take higher precedence than this signal. It triggers L1 exit but the link transits back to L1 again from L0 if the D3 state is not cleared.

This is a level-sensitive signal.

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