F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 10/04/2022
Public
Document Table of Contents

7.3. Endpoint Testbench

The example design and testbench are dynamically generated based on the configuration that you choose for the F-Tile IP for PCIe. The testbench uses the parameters that you specify in the Parameter Editor in Intel® Quartus® Prime.

This testbench simulates up to a x16 PCI Express link using the serial PCI Express interface. The testbench design does allow more than one PCI Express link to be simulated at a time. The following figure presents a high level view of the design example.
Figure 66. Design Example for Endpoint Designs

The top-level of the testbench instantiates the following main modules:

  • altpcietb_bfm_rp_gen4_x16.sv —This is the Root Port PCIe* BFM.
    //Directory path
    <project_dir>/pcie_avst_f_0_example_design/pcie_ed_tb/ip/pcie_ed_tb/dut_pcie_tb_ip/intel_pcie_ftile_tbed_<ver>
  • pcie_ed_dut.ip: This is the Endpoint design with the parameters that you specify.
    //Directory path
    <project_dir>/pcie_avst_f_0_example_design/ip/pcie_ed
  • pcie_ed_pio0.ip: This module is a target and initiator of transactions for the PIO design example.
    //Directory path
    <project_dir>/intel_pcie_ftile_ast_0_example_design/ip/pcie_ed

In addition, the testbench has routines that perform the following tasks:

  • Generates the reference clock for the Endpoint at the required frequency.
  • Provides a PCI Express reset at start up.

For more details on the PIO design example testbench and SR-IOV design example testbench, refer to the Intel FPGA F-Tile Avalon® streaming IP for PCI Express Design Example User Guide.

Note: By default, the serial_sim_hwtcl parameter in <project_dir>/pcie_avst_f_0_example_design/pcie_ed_tb/ip/pcie_ed_tb/dut_pcie_tb_ip/intel_pcie_ftile_tbed_<ver>/sim/intel_pcie_ftile_tbed_hwtcl.v is set to 1 for serial simulation. F-Tile does not support parallel PIPE simulations.

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