F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 10/04/2022
Public
Document Table of Contents

4.2.6. Malformed TLP

In TLP Bypass mode, a malformed TLP is dropped in the F-Tile AVST IP for PCIe and its event is logged in the AER capability registers. F-Tile also notifies user of this event by asserting the serr_out_o signal. Refer to the PCI Express Base Specification for the definition of a malformed TLP.

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