F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 10/04/2022
Public
Document Table of Contents

6.2. Core Parameters

Depending on which Hard IP Mode you choose in the Top-Level Settings tab, you will see different tabs for setting the core parameters.

Figure 59. Intel F-Tile Avalon® -ST Top-Level IP Parameter Editor for a 1 x16 Hard IP Mode If you choose a 1 x16 mode (either Gen4 or Gen3), only the PCIe0 Settings tab will appear.
Figure 60. Intel F-Tile Avalon® -ST Top-Level IP Parameter Editor for a 2 x8 Hard IP Mode If you choose a 2 x8 mode (either Gen4 or Gen3), the PCIe0 Settings and PCIe1 Settings tabs will appear.
Figure 61. Intel F-Tile Avalon® -ST Top-Level IP Parameter Editor for a 4 x4 Hard IP Mode If you choose a 4 x4 mode (either Gen4 or Gen3), the PCIe0 Settings, PCIe1 Settings, PCIe2 Settings and PCIe3 Settings tabs will appear.
Note: You can enable the TLP Bypass mode in the Top-Level Settings tab of the IP Parameter Editor as shown in the figure below:
Figure 62. Enabling TLP Bypass Mode

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