F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 10/04/2022
Public
Document Table of Contents

8.1.1.3. Additional Debug Tools

Use the Hard IP reconfiguration interface and PHY reconfiguration interface on the F-Tile Avalon® -ST IP for PCI Express to access additional registers (for example, receiver detection, lane reversal etc.).

Figure 74. Register Access for Debug

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