F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 10/04/2022
Public
Document Table of Contents

5.7. Error Interface

This is an optional interface in the Intel F-Tile Avalon-ST IP for PCI Express that allows the Application Layer to report errors to the IP core and vice versa. Specifically, the Application Layer can report the different types of errors defined by the app_error_info_i signal to the IP. For Advanced Error Reporting (AER), the Application Layer can provide the information to log the TLP header and the error log request via the app_err_* interface.

The Intel F-Tile Avalon-ST IP for PCI Express enables the AER capability for Physical Functions (PFs) by default. There is no AER implementation for Virtual Functions (VFs). Use the VF Error Flag Interface instead of AER when using VFs.

Note: The Error Interface is not available for Topology H.
Table 68.  Error Interface Signals
Signal Name Direction EP/RP/BP Clock Domain Description
p#_serr_out_o Output EP/RP/BP coreclkout_hip

Indicates system error is detected.

RP mode: A one-clock-cycle pulse on this signal indicates if any device in the hierarchy reports any of the following errors and the associated enable bit is set in the Root Control register: ERR_COR, ERR_FATAL, ERR_NONFATAL.

Also asserted when an internal error is detected. The source of the error will be logged in the Root Port Error Status registers in the Port Configuration and Status registers.

EP mode: Asserted when the F-Tile PCIe Hard IP sends a message of correctable/non-fatal/fatal error.

BP mode: The transaction layer or data link layer errors detected by the Hard IP core trigger this signal. Detailed information are logged in the Bypass Mode Error Status registers in the Port Configuration and Status registers.

p#_hip_enter_err_mode_o Output EP/RP/BP coreclkout_hip

Asserted when the Hard IP enters the error mode. This usually happens when the Hard IP detects an uncorrectable RAM ECC error. Upon seeing the assertion of this signal, user should discard all the TLPs received.

p#_app_err_valid_i Input EP/RP coreclkout_hip

A one-cycle pulse on this signal indicates that the data on app_err_info_i, app_err_hdr_i, and app_err_func_num_i are valid in that cycle and app_err_hdr_i will be valid during the following four cycles.

p#_app_err_hdr_i[31:0] Input EP/RP coreclkout_hip

This bus contains the header and TLP prefix information for the error TLP. The 128-bit header and 32-bit TLP prefix are sent to the Hard IP over five cycles (32 bits of information are sent in each clock cycle).

Cycle 1 : header[31:0]

Cycle 2 : header[63:32]

Cycle 3 : header[95:64]

Cycle 4 : header[127:96]

Cycle 5 : TLP prefix

p#_app_err_info_i[12:0] Input EP/RP coreclkout_hip
This error bus carries the following information:
  • [0]: Malformed TLP
  • [1]: Receiver overflow
  • [2]: Unexpected completion
  • [3]: Completer abort
  • [4]: Completion timeout
  • [5]: Unsupported request
  • [6]: Poisoned TLP received
  • [7]: AtomicOp egress blocked
  • [8]: Uncorrectable internal error
  • [9]: Correctable internal error
  • [10]: Advisory error
  • [11]: TLP prefix blocked
  • [12]: ACS violation
p#_app_err_func_num_i[2:0] Input EP coreclkout_hip
Note: Not available for p2 and p3.

This bus contains the function number for the function that asserts the error valid signal.

Figure 57. Error Interface Timing Diagram
For Topology H [1x4], error reporting is via the Hard IP Reconfiguration Interface. Your application needs to write to the APP_ERR registers follow the steps listed below.
  1. Write the error TLP header [127:96] to APP_ERR_HDR3 register
  2. Write the error TLP header [95:64] to APP_ERR_HDR2 register
  3. Write the error TLP header [63:32] to APP_ERR_HDR1 register
  4. Write the error TLP header [31:0] to APP_ERR_HDR0 register
  5. Write the error TLP prefix to APP_ERR PRFX register
  6. Write error valid, error function number, and error information to APP_ERR_BUS register
Table 69.  APP_ERR regsiters for Topology H
Register Offset Address Bit Description Access Type Default Value
APP_ERR_HDR0 0x14300 31:0 TLP header [31:0] RW 0x0000_0000
APP_ERR_HDR1 0x14304 31:0 TLP header [63:32] RW 0x0000_0000
APP_ERR_HDR2 0x14308 31:0 TLP header [95:64] RW 0x0000_0000
APP_ERR_HDR3 0x1430C 31:0 TLP header [127:96] RW 0x0000_0000
APP_ERR_PRFX 0x14310 31:0 TLP prefix RW 0x0000_0000
APP_ERR_BUS 0x14314 31:17 RSVD RO 0x0000
16:4

Error Information

Note: Refer to the error information defined for p#_app_err_info_i in Error Interface Signals Table
RW 0x0000
3:1 Function Number RW 0x0
0 Valid RW 0x0
Figure 58. Topology H Error Interface Hard IP Write

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