F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 10/04/2022
Public
Document Table of Contents

7.6.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task

The ebfm_log_set_stop_on_msg_mask procedure controls which message types stop simulation. This procedure alters the default behavior of the simulation when errors occur as described in the BFM Log and Message Procedures.

Location

 

Syntax

ebfm_log_set_stop_on_msg_mask (msg_mask)

Argument

msg_mask

This argument is reg [EBFM_MSG_ERROR_CONTINUE:EBFM_MSG_DEBUG].

A 1 in a specific bit position of the msg_mask causes messages of the type corresponding to the bit position to stop the simulation after the message is displayed.

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