F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 10/04/2022
Public
Document Table of Contents

A.2.2.4.4. Egress Control Vector (Offset 0x8)

Table 138.  Egress Control Vector
Bits Register Description Default Value Access
[31:0] Egress Control Vector 0x0 RO

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