F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 10/04/2022
Public
Document Table of Contents

6.2.3. PCI Express and PCI Capabilities Parameters

For each core (PCIe0/PCIe1/PCIe2/PCIe3), the PCI Express / PCI Capabilities tab contains separate tabs for the device, PRS (Endpoint mode), MSI (Endpoint mode), ACS capabilities (Root Port mode), slot (Root Port mode), MSI-X, and legacy interrupt pin register parameters.

Figure 63. PCI Express / PCI Capabilities Parameters

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