The F-Tile Avalon® Streaming Interface for PCI Express supports the following features:
- Complete protocol stack including the Transaction, Data Link and Physical Layers implemented as a Hard IP.
- Topologies supported:
Table 2. Topologies Supported Gen3/Gen4 x16 Gen3/Gen4 x8 Gen3/Gen4 x4 Endpoint
YesNote: Gen1/Gen2 or lower link width configurations are supported via link down-training
- Supports up to 512-byte maximum payload size (MPS).
- Supports Single Virtual Channel (VC).
- Supports Completion Timeout Ranges through Completion Timeout Interface
- Atomic Operations (FetchAdd/Swap/CAS).
- Extended Tag Support. (10-bit Tag Support Applies to x16 ports only. Maximum 512 Outstanding Non-Posted Request)
- Separate Refclk with Independent Spread Spectrum Clocking (SRIS).
- Separate Refclk with no Spread Spectrum Clocking (SRNS).
- Common Refclk architecture.
- PCI Express* Advanced Error Reporting (Physical Function only).
- ECRC generation and checking.
- Data bus parity protection.
- Supports D0 and D3 PCIe power states.
- Lane Margining at Receiver.
- Retimers presence detection.
Multifunction and Virtualization Features:
- Single Root-IO Virtualization (SRIOV). Up to 2048 Virtual Functions.
- ACS Control Service (ACS) capability support for Port 0 and 1 (x16 Core and x8 Core)
- Alternative Routing-ID Interpretation (ARI).
- Function Level Reset (FLR).
- TLP Processing Hint (TPH).
Note: TPH supports the "No Steering Tag (ST)" mode only.
- Address Translation Services (ATS)
- Supports Page Request Services (PRS).
- Process Address Space ID (PASID).
- Configuration Intercept Interface (for VirtIO).
Avalon® Streaming Interface IP Features:
- User packet interface with separate header, data and prefix.
- User packet interface with a split-bus architecture where the header, data and prefix busses consist of two segments each (x16 mode only). This improves the bandwidth efficiency of this interface as it can handle up to 2 TLPs in any given cycle.
- Up to 512 outstanding Non-Posted request for Port 0 (x16 core)
- Up to 256 outstanding Non-Posted request for Port 1,2 and 3 (x8 and x4 cores)
- Supports Autonomous Hard IP mode. This mode allows the PCIe Hard IP to communicate with the Host before the FPGA configuration and entry into user mode are complete.
Note: Unless Readiness Notifications mechanisms are used, the Root Complex and/or system software must allow at least one second after a Conventional Reset of a device before it may determine that a device that fails to return a Successful Completion status for a valid Configuration Request is a broken device. This period is independent of how quickly Link training is complete.
- FPGA core configuration via PCIe link (CvP Init and CvP Update) supported by the x16Core or Port 0 only
- Variable PLD clock frequencies: (500 MHz/ 450 MHz / 400 MHz / 350 MHz / 250 MHz / 225 MHz / 200 MHz /175 MHz for Intel® Agilex™ )
- Legacy Interrupts
- MSI/MSI-X interrupts
- Configuration Extension Bus & VSEC via CII interface
Note: CII Interface is not supported for 1 x4 configuration or Topology H.
- Precision Time Measurement (PTM) (PTM Requester only)
Note: You can enable PTM only in one core (either x16 or x8) at any given time.
- Parity Support on Avalon-ST interface
- The FPGA pin allocations for the F-Tile Avalon Streaming IP for PCI Express in the Intel® Quartus® Prime project is fixed. However, this IP does support lane reversal and polarity inversion on the PCB by default.
- VCS* , VCS* MX, QuestaSim* and Xcelium* are the simulators supported in the current Intel® Quartus® Prime release. Other simulators may be supported in a future release.
Standards and Specification Compliance
- PCI Express Base Specification Revision 4.0
- Single Root I/O Virtualization and Sharing Specification, Rev 1.1
- Address Translation Services, Revision 1.1
- PHY Interface for PCI Express Architectures, Version 4.x (the spec that corresponds to PCI Express Base Spec, Revision 4.0)
- Virtual I/O Device (VIRTIO) Version 1.0
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