F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 10/04/2022
Public
Document Table of Contents

5.16. Page Request Service (PRS) Interface (EP Only)

Table 78.  Page Request Service (PRS) Interface Signals
Signal Name Direction EP/RP/BP Clock Domain Description
p#_prs_event_valid_i Input EP coreclkout_hip

Note: Not available for p2 and p3.

This signal qualifies prs_event_func_i and prs_event_i. There is a single-cycle pulse for each PRS event.

p#_prs_event_func_i[2:0] Input EP coreclkout_hip

Note: Not available for p2 and p3.

The function number for the PRS event.

p#_prs_event_i[1:0] Input EP coreclkout_hip

Note: Not available for p2 and p3.

00 : Indicates that the function has received a PRG response failure.

01: Indicates that the function has received a response with Unexpected Page Request Group Index.

10: Indicates that the function has completed all previously issued pagerequests and that it has stopped requests for additional pages. Only valid when the PRS enable bit is clear.

11: reserved.

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