F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 10/04/2022
Document Table of Contents

E.2.3. Configuration Type C

System Clock obtains a free running clock. Port 0 gets a free running reference clock.

Port 0 is required to support CVP_INIT and CVP_UPDATE so that Port 0’s perst must be set to pin_perst_n.

Port 1 gets the RefClk from the Host where the RefClk is power gateable. This clock turns off when PERST# is asserted and it will be stable prior to PERST# deassertion.

Figure 103. 2 Host with one port using pin_perst and another port using gpio_perst

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