F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide
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Ixiasoft
6.2.3.5. MSI-X Capabilities
Parameter | Value | Default Value | Description |
---|---|---|---|
Enable MSI-X (Endpoint only) | True/False | False | Enables the MSI-X functionality. |
MSI-X Table Size | 0x0 - 0x7FF (only values of powers of two minus 1 are valid) | 0 | System software reads this field to determine the MSI-X table size <n>, which is encoded as <n-1>. For example, a returned value of 2047 indicates a table size of 2048. This field is read-only. Address offset: 0x068[26:16] |
MSI-X Table Offset | 0x0 - 0xFFFFFFFF | 0 | Points to the base of the MSI-X table. The lower 3 bits of the table BAR indicator (BIR) are set to zero by software to form a 64-bit qword-aligned offset. This field is read-only after being programmed. |
Table BAR indicator | 0x0 - 0x5 | 0 | Specifies which one of a function's BARs, located beginning at 0x10 in Configuration Space, is used to map the MSI-X table into memory space. This field is read-only after being programmed. |
Pending bit array (PBA) offset | 0x0 - 0xFFFFFFFF | 0 | Used as an offset from the address contained in one of the function's Base Address registers to point to the base of the MSI-X PBA. The lower 3 bits of the PBA BIR are set to zero by software to form a 32-bit qword-aligned offset. This field is read-only after being programmed. |
PBA BAR indicator | 0x0 - 0x5 | 0 | Specifies the function's Base Address register, located beginning at 0x10 in Configuration Space, that maps the MSI-X PBA into memory space. This field is read-only after being programmed. |
VF Table size | 0x0 - 0x7FF (only values of powers of two minus 1 are valid) | 0 | Sets the number of entries in the MSI-X table for VFs. MSI-X cannot be disabled for VFs. Set to 1 to save resources. |