F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 10/04/2022
Public
Document Table of Contents

5.3. Serial Data Interface

Table 60.  Serial Data Interface Signals
Signal Name Direction EP/RP/BP Description

tx_p_out[b-1:0]

tx_n_out[b-1:0]

Output EP/RP/BP Trasnmit serial data output using High Speed Differential I/O Standard

rx_p_in[b-1:0]

rx_n_in[b-1:0]

Input

EP/RP/BP

Receive serial data output using High Speed Differential I/O Standard

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