F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 10/04/2022
Public
Document Table of Contents

3.1.1. Clocks

The F-Tile IP for PCI Express has three primary clock domains:
  • PHY clock domain (core_clk domain): This clock is synchronous to the SerDes parallel clock.
  • EMIB/FPGA fabric interface clock domain (pld_clk domain): This clock is generated from a System PLL. The System PLL could share the same reference clock used by the SerDes or a separate reference clock.
  • Application clock domain (coreclkout_hip): this clock is an output from the F-Tile IP, and it has the same frequency as pld_clk.
Figure 3. Clock Domains

The PHY clock domain (core_clk domain) is a dynamic frequency domain. The PHY clock frequency is dependent on the current link speed.

Table 9.  PHY Clock and Application Clock Frequencies
Link Speed PHY Clock Frequency Application Clock Frequency
Gen1 125 MHz

Gen1 is supported only via link downtraining and not natively. Hence, the application clock frequency depends on the configuration you select in the IP Parameter Editor. For example, if you select a Gen3 configuration, the application clock frequency is 250 MHz.

Gen2 250 MHz

Gen2 is supported only via link downtraining and not natively. Hence, the application clock frequency depends on the configuration you select in the IP Parameter Editor. For example, if you select a Gen3 configuration, the application clock frequency is 250 MHz.

Gen3 500 MHz 250 MHz
Gen4 1000 MHz 500 MHz / 450 MHz / 400 MHz / 350 MHz / 250 MHz / 225 MHz / 200 MHz / 175 MHz
Note: As the data width remains unchanged, using lower frequency results in lower data throughput.
Note: For a link down-training scenario when the F-Tile is configured at Gen3 or Gen4 and the link gets down-trained to a lower speed, the application clock frequency continues to run at the configured frequency set in the PLD Clock Frequency parameter. For example, the PCIe Hard IP Mode parameter is set as Gen4 1x16 and the PLD Clock Frequency parameter as 500 MHz, the PLD clock frequency continues to run at 500 MHz even if the Link is down trained to Gen 3 or less.

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