F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 10/04/2022

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Document Table of Contents

10. Revision History for the F-Tile Avalon Streaming Intel FPGA IP for PCI Express User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2022.10.04 22.3 7.0.0
Sections Updated:
2022.07.14 22.2 6.0.0
  • Features: Variable PLD clock frequencies updated in Avalon Streaming Interface IP Features
  • Release Information: IP Version & Intel® Quartus® Prime version updated
  • Performance and Resource Utilization: Recommended FPGA Fabric Speed Grades for All Avalon-ST Widths and Frequencies table updated
  • IP Core and Design Example Support Levels: F-Tile Avalon Streaming (Avalon-ST) IP for PCIe Support Matrix for Intel® Agilex™ Devices table updated
  • Overview: IP to FPGA Fabric Interfaces Summary table updated
  • Top-Level Settings: Rows in table updated Hard IP Mode and PLD Clock Frequency
  • Avalon Parameters: New row added in table Enable Hard IP Reconfiguration Interface
  • FASTSIM Mode Support: New section added
  • Overview: Debug Toolkit description added
  • Eye Viewer: Note added
2022.04.04 22.1 5.0.0
  • Release Information updated for Intel® Quartus® Prime 22.1
  • 450 MHz [Clock Frequency] and -3 [Speed Grade] support added in Performance and Resource Utilization
  • Reset section description updated
  • Avalon-ST TX description updated
  • Options to implement Device ID and Vendor ID information added in Avalon-MM usage for TLP Bypass Mode
  • Enable Independent Perst parameter added in Top Level Settings table in Top-Level Settings
  • PIPE PhyStatus parameter information added in F-Tile Information
  • Eye Viewer description updated
  • New Appendix added Bifurcated Endpoint Support for Independent Resets
2021.12.17 21.4 4.0.0
  • Release Information table updated for Intel® Quartus® Prime 21.4 release
  • Resource Utilization Information of the IP table added
  • TLP Bypass Mode section added to Advanced Features Chapter
  • F-Tile Debug Toolkit paramter information added to Top Level Settings table in Parameters Chapter
  • Screenshots updated in Core Parameters section of Parameters Chapter
  • Generating Tile Files information added to Testbench Chapter
  • Address Offsets and Bit Settings to enable and read LCRC and ECRC error count table updated
  • Example: To read the LCRC error count of x16 Port 0 using the registers steps updated
  • Debug Toolkit information added to Troubeshooting/Debugging Chapter
2021.10.22 21.3 3.0.0
  • RX Flow Control description updated
  • Buffer Limits Update example Figure updated in RX Flow Control
  • Credit Advertised by F-Tile PCIe Hard IP table added in RX Flow Control
  • Power Management section updated with new description
  • Variables Used in the Bus Indices Table updated
  • Timing Diagrams and tables added in Error Interface
  • 10-bit Tag Support Interface new section added
  • Power Management Interface Signals table updated in Power Management Interface
  • Hard IP Reconfiguration Interface Register Map for PHY Status table updated in AdditionalDebug Tools
  • Core Parameters section updated
  • Information to enable and read LCRC and ECRC error count added in Enable and Read LCRC and ECRC Error Count
  • New Appendix added Root Port Enumeration
2021.08.27 21.2 2.0.0 Initial Release