F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 10/04/2022
Public
Document Table of Contents

E.2.2. Configuration Type B

System Clock obtains a free running clock.

Port 0 and Port 1 gets the RefClk from the Host where the RefClk is power gateable. This clock turns off when PERST# is asserted and it will be stable prior to PERST# deassertion.

Figure 102. 2 Host with reference clocks from the Host

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