F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 10/04/2022
Public
Document Table of Contents

A.2.2.3.2. ATS Capability Register and ATS Control Register (Offset 0x4)

The lower 16 bits of this location make up the ATS Capability Register, and the upper 16 bits make up the ATS Control Register.

Table 134.  ATS Capability Register and ATS Control Register
Bits Register Description Default Value Access
[4:0]

Invalidate Queue Depth: The number of Invalidate Requests that the Function can accept before throttling the upstream connection. If 0, the Function can accept 32 Invalidate Requests.

This field is hardwired to 0 for VFs. VFs use the setting from the parent PF’s ATS Capability Register.

0x0 RO
[5] Page Aligned Request: If set, indicates the untranslated address is always aligned to a 4096-byte boundary. This bit is hardwired to 1. 0x1 RO
[15:6] Reserved 0x0 RO
[20:16]

Smallest Translation Unit (STU): This value indicates to the Function the minimum number of 4096-byte blocks specified in a Translation Completion or Invalidate Request. This is a power of 2 multiplier. The number of blocks is 2STU. A value of 0 indicates one block and a value of 0x1F indicates 231 blocks, or 8 terabytes (TB) total.

This field is hardwired to 0 for VFs. VFs use the setting from the parent PF’s ATS Control Register.

0x0 RO
[30:21] Reserved 0x0 RO
[31]

Enable (E) bit. When Set, the Function can cache translations.

You need to obtain this information from configuration intercept interface.

0x0 RW

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