F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 10/04/2022
Public
Document Table of Contents

5.5.2. MSI Pending Bits Interface Signals

Table 66.  MSI Pending Bits Interface Signals
Signal Name Direction EP/RP/BP Clock Domain Description
p#_msi_pnd_func_i[2:0] Input EP coreclkout_hip

Note: Not available for p2 and p3.

Function number select for the Pending Bits register in the MSI capability structure.

p#_msi_pnd_addr_i[1:0] Input EP coreclkout_hip

Note: Not available for p2 and p3.

Byte select for Pending Bits Register in the MSI Capability Structure.

For example if msi_pnd_addr_i[1:0] = 00, bits [7:0] of the Pending Bits register will be updated with msi_pnd_byte_i[7:0].

If msi_pnd_addr_i[1:0] = 01, bits [15:8] of the Pending Bits register will be updated with msi_pnd_byte_i[7:0].

p#_msi_pnd_byte_i[7:0] Input EP coreclkout_hip

Note: Not available for p2 and p3.

Indicate that function has apending associated message.

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