F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 10/04/2022
Public
Document Table of Contents

5.5.1. Legacy Interrupt Interface Signals

Table 65.  Legacy Interrupt Interface Signals
Signal Name Direction EP/RP/BP Clock Domain Description
p#_app_int_i[7:0] Input EP coreclkout_hip

Note: Not available for p2 and p3.

When asserted, these signals indicate an assertion of an INTx message is requested. A transition from high to low indicates a deassertion of the INTx message is requested.

This bus is for EP only. Each bit is associated with a corresponding physical function. These signals must be asserted for at least 8 cycles.

p#_int_status_o Output RP coreclkout_hip

These signals drive legacy interrupts to the Application Layer in Root Port mode.

The source of the interrupt will be logged in the Root Port Interrupt Status registers in the Port Configuration and Status registers.

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