F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 10/04/2022
Public
Document Table of Contents

3.9. Configuration Intercept Interface (EP Only)

The Configuration Intercept Interface (CII) allows the application logic to detect the occurrence of a Configuration (CFG) request on the link and to modify its behavior. The application logic detects the CFG request at the rising edge of cii_req. Due to the latency of the EMIB, the cii_req can be deasserted many cycles after the deassertion of cii_halt.

Note: CII Interface is not supported for 1 x4 configuration or Topology H.
Note: CII interface is supported in 1x4 with all ports, except p0_cii_dout_o, p0_cii_override_en_i, and p0_cii_override_din_i.
The application logic can use the CII to:
  • Delay the processing of a CFG request by the controller. This allows the application to perform any housekeeping task first.
  • Overwrite the data payload of a CfgWr request. The application logic can also overwrite the data payload of a CfgRd completion TLP.

This interface also allows you to implement the Vendor Specific Extended Capability (VSEC) registers. Example of such implementation is described in following section.

If you are not using this interface, tie cii_halt_i to logic 0.

The following Configuration access is not visible on CII due to internal IP function.
  • Read to last PF's ARI Capability and Control Register.
The following Configuration access is not visible on CII due to VIRTIO Capability Register implementation in soft logic.
  • All Read/Write access to PF/VF VIRTIO Capability register range.

Figure 38. Configuration Intercept Interface Timing Diagram

Implementing Vendor Specific Extended Capability (VSEC) Registers

The following flow chart describes the recommended steps for user to implement Vendor Specific Extended Capability registers.
Note: Both Subroutine that is filled with RED color AND texts that are RED font, are optional.
Figure 39. Implementing Vendor Specific Extended Capability (VSEC) Registers

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