F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 10/04/2022
Public
Document Table of Contents

6.2.3.6. Slot Capabilities

Note: This tab is visible in the Parameter Editor only if the Port Mode parameter in the Top-Level Settings tab is set to Root Port.
Table 92.  Slot Capabilities
Parameter Value Default Value Description
Use Slot register True/False False

This parameter is only supported in Root Port mode. The slot capability is required for Root Ports if a slot is implemented on the port. Slot status is recorded in the PCI Express Capabilities register.

Slot power scale 0 - 3 0
Specifies the scale used for the slot power limit. The following coefficients are defined:
  • 0 = 1.0x
  • 1 = 0.1x
  • 2 = 0.01x
  • 3 = 0.001x

The default value prior to hardware and firmware initialization is b’00. Writes to this register also cause the port to send the Set_Slot_Power_Limit message.

Slot power limit 0 - 255 0 In combination with the Slot power scale value, specifies the upper limit in watts for the power supplied by the slot.
Slot number 0 - 8191 0 Specifies the slot number.

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