F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 10/04/2022
Public
Document Table of Contents

8.2.1. Overview

The F-Tile Debug Toolkit is a System Console-based tool for F-Tile that provides real-time control, monitoring and debugging of the PCIe links at the Physical Layer.

The F-Tile Debug Toolkit allows you to:

  • View protocol and link status of the PCIe links.
  • View PLL and per-channel status of the PCIe links.
  • View the channel analog settings.
  • Indicate the presence of a re-timer connected between the link partners.
Note: The current version of Intel® Quartus® Prime supports enabling the Debug Toolkit for the Endpoint mode only, and with the Linux and Windows operating systems only.

The following figure provides an overview of the F-Tile Debug Toolkit in the F-Tile Avalon® -ST IP for PCI Express.

Figure 75. Overview of the F-Tile Debug Toolkit

When you enable the F-Tile Debug Toolkit, the intel_pcie_ftile_ast module of the generated IP includes the Debug Toolkit modules and related logic as shown in the figure above.

Drive the Debug Toolkit from a System Console. The System Console connects to the Debug Toolkit via an Native PHY Debug Master Endpoint (NPDME). Make this connection via an Intel FPGA Download Cable.

When the Debug Toolkit is enabled, a multiplexer is implemented to allow dynamic switching between the user AVMM reconfiguration interface and the System Console-based Debug Toolkit. This allows you to switch between the user logic driving the reconfiguration interface and the Debug Toolkit, as both access the same set of registers within the Hard IP.

Note: The user AVMM reconfiguration interface has the default access (the default is when toolkit_mode = 0). Upon launching the Debug Toolkit from System Console, toolkit_mode is automatically set to 1 for DTK access. Upon exiting (closing) the Debug Toolkit window of the System Console, toolkit_mode is automatically set to 0 for user access.

The Debug Toolkit is launched successfully only if pending read/write transactions on the reconfiguration interface are completed (as indicated by the deassertion of the reconfig_waitrequest signal).

Note: Upon being launched from System Console, the Debug Toolkit will first check if any of the waitrequest signals from the Hard IP is asserted (which means there is an ongoing request from you). The System Console message window shows an error message to let you know there is an ongoing request and the Debug Toolkit cannot be launched.
The PHY reconfiguration interface clock (xcvr_reconfig_clk) is used to clock the following interfaces:
  • The NPDME module
  • PHY reconfiguration interface (xcvr_reconfig)
  • Hard IP reconfiguration interface (hip_reconfig)

Provide a clock source (50 MHz - 125 MHz, 100 MHz recommended clock frequency) to drive the xcvr_reconfig_clk clock. Use the output of the Reset Release Intel FPGA IP to drive the ninit_done, which provides the reset signal to the NPDME module.

Note: When you enable the F-Tile Debug Toolkit, the Hard IP Reconfiguration interface is enabled by default.
When you run a dynamically-generated design example on the Intel Development Kit, make sure that clock and reset signals are connected to their respective sources and appropriate pin assignments are made. Here are some sample .qsf assignments for the Debug Toolkit:
  • set_location_assignment PIN_C23 -to xcvr_reconfig_clk_clk

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