F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 10/04/2022
Public
Document Table of Contents

7.6.7. ebfm_cfgrd_wait Procedure

The ebfm_cfgrd_wait procedure reads up to four bytes of data from the specified configuration register and stores the data in BFM shared memory. This procedure waits until the read completion has been returned.

Location

 

Syntax

ebfm_cfgrd_wait(bus_num, dev_num, fnc_num, regb_ad, regb_ln, lcladdr, compl_status)

Arguments

bus_num

PCI Express bus number of the target device.

dev_num

PCI Express device number of the target device.

fnc_num

Function number in the target device to be accessed.

regb_ad

Byte-specific address of the register to be written.

regb_ln

Length, in bytes, of the data read. Maximum length is four bytes. The regb_ln and the regb_ad arguments cannot cross a DWORD boundary.

lcladdr

BFM shared memory address of where the read data should be placed.

compl_status

Completion status for the configuration transaction.

This argument is reg [2:0].

In both languages, this is the completion status as specified in the PCI Express specification. The following encodings are defined.

  • 3’b000: SC— Successful completion
  • 3’b001: UR— Unsupported Request
  • 3’b010: CRS — Configuration Request Retry Status
  • 3’b100: CA — Completer Abort

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