F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 10/04/2022
Public
Document Table of Contents

5.1. Overview

By looking at the prefix of the signal names, you can determine the port origin of the signal.
  • p0: x16 core
  • p1: x8 core
  • p2: x4_0 core
  • p3: x4_1 core

The figure below shows the top-level signals of this IP. Note that the signal names in the figure will get the appropriate prefix pn (where n = 0, 1, 2 or 3) depending on which of the three supported configurations (1x16, 2x8, or 4x4) the F-Tile Avalon-ST IP for PCI Express is present.

As an example, the rx_st_data_o bus can take on the following names:
  • In the 1x16 configuration, only the x16 core is active. In this case, this bus appears as p0_rx_st_data_o[511:0].
  • In the 2x8 configuration, both the x16 core and x8 core are active. In this case, this bus is split into p0_rx_st_data_o[255:0] and p1_rx_st_data_o[255:0].
  • In the 4x4 configuration, all four cores are active. In this case, this bus is split into p0_rx_st_data_o[127:0], p1_rx_st_data_o[127:0], p2_rx_st_data_o[127:0] and p3_rx_st_data_o[127:0].

The only cases where the interface signal names do not get the pn prefixes are the interfaces that are common for all the cores, like the PHY reconfiguration interface, clocks and resets. For example, there is only one xcvr_reconfig_clk that is shared by all the cores.

You can enable the PHY reconfiguration interface from the Top Level Settings in the GUI.

Each of the cores has its own Avalon-ST interface to the user logic. The number of IP-to-User Logic interfaces exposed to the FPGA fabric are different based on the configuration modes.

Table 56.  IP to FPGA Fabric Interfaces Summary
Mode Avalon-ST Interface Count Data Width (each Interface) Header Width (each Interface) TLP Prefix Width (each Interface) Application Clock Frequency
Gen4 x16 1 512-bit 256-bit 64-bit 175 MHz / 200 MHz / 225 MHz / 250 MHz / 350 MHz / 400 MHz / 450 MHz / 500 MHz (1)
Gen4 x8 1 256-bit 128-bit 32-bit 350 MHz / 400 MHz / 450 MHz /500 MHz(1)
Gen4 x8x8 2 512-bit(3) 256-bit 64-bit 175 MHz / 200 MHz / 225 MHz / 250 MHz(1)
256-bit 128-bit 32-bit 175 MHz / 200 MHz / 225 MHz / 250 MHz / 350 MHz / 400 MHz / 450 MHz / 500 MHz(1)
Gen4 x4 1 128-bit 128-bit 32-bit 350 MHz / 400 MHz / 450 MHz /500 MHz(1)
Gen4 x4x4 2 128-bit 128-bit 32-bit 350 MHz / 400 MHz / 450 MHz /500 MHz(1)
Gen4 x4x4x4x4 4 128-bit 128-bit 32-bit 350 MHz / 400 MHz / 450 MHz /500 MHz(1)
Gen3 x16 1 512-bit 256-bit 64-bit 250 MHz
256-bit(2) 128-bit 32-bit 250 MHz
Gen3 x8 1 256-bit 128-bit 32-bit 250 MHz
Gen3 x8x8 2 256-bit 128-bit 32-bit 250 MHz
Gen3 x4 1 128-bit 128-bit 32-bit 250 MHz
Gen3 x4x4 2 128-bit 128-bit 32-bit 250 MHz
Gen3 x4x4x4x4 4 128-bit 128-bit 32-bit 250 MHz
Note:
  1. Select the highest clock frequency to achieve maximum PCIe Gen4 bandwidth.
  2. In this configuration, interface efficiency is traded off for lower interface width.
  3. In this configuration, interface width increased to support lower application clock frequency.
Figure 56. F-Tile Avalon-ST IP for PCI Express Top-Level Signals

The following variables will be used to differentiate signal width differences between different cores and different topology.

Table 57.  Variables Used in the Bus Indices
Variable 1x16 Configuration 2x8 Configuration 1x8 Configuration 4x4 Configuration 2x4 Configuration 1x4 Configuration
w 4 2 2 1 1 1
n 2 1 1 1 1 1
p 6 3 3

3

2 for p#_rx_st_empty_o

3

2 for p#_rx_st_empty_o

3

2 for p#_rx_st_empty_o

c 8 8 8

8 for Port 0 and 1

1 for Port 2 and 3

8 for Port 0

1 for Port 2

8
b 16 16 8 16 8 4
# 0 0,1 0 0,1,2,3 0,2 0
  • EP= Applicable to EndPoint Mode.
  • RP= Applicable to Root Port Mode.
  • BP= Applicable to TLP Bypass mode.

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