Altera® Quartus® Prime Standard Edition Settings File Reference Manual

ID 683084
Date 5/08/2017
Public
Document Table of Contents

1.2.63. FORCE_SYNCH_CLEAR

Forces the Compiler to utilize synchronous clear signals in normal mode logic cells. Turning on this option helps to reduce the total number of logic cells used in the design, but might negatively impact the fitting since synchronous control signals are shared by all the logic cells in a LAB.

Type

Boolean

Device Support

  • Arria 10
  • Arria GX
  • Arria II GX
  • Arria II GZ
  • Arria V
  • Arria V GZ
  • Cyclone
  • Cyclone 10 LP
  • Cyclone II
  • Cyclone III
  • Cyclone III LS
  • Cyclone IV E
  • Cyclone IV GX
  • Cyclone V
  • HardCopy II
  • HardCopy III
  • HardCopy IV
  • MAX 10
  • MAX II
  • MAX V
  • Stratix
  • Stratix GX
  • Stratix II
  • Stratix II GX
  • Stratix III
  • Stratix IV
  • Stratix V

Notes

This assignment is included in the Analysis & Synthesis report.

This assignment supports synthesis wildcards.

Syntax


		set_global_assignment -name FORCE_SYNCH_CLEAR <value>
		set_global_assignment -name FORCE_SYNCH_CLEAR -entity <entity name> <value>
		set_instance_assignment -name FORCE_SYNCH_CLEAR -to <to> -entity <entity name> <value>
	

Default Value

Off

Example


		set_global_assignment -name force_synch_clear on
		set_instance_assignment -name force_synch_clear on -to foo
	

See Also

Allow Synchronous Control Signals