Altera® Quartus® Prime Standard Edition Settings File Reference Manual

ID 683084
Date 5/08/2017
Public
Document Table of Contents

1.2.1. ADV_NETLIST_OPT_ALLOWED

Specifies whether the Compiler should perform advanced netlist optimizations, such as gate-level retiming or physical synthesis, on the specified node or entity. If this option is set to 'Default', the Compiler duplicates, moves, or changes the synthesis of the node or entity, or allows register retiming during netlist optimization, only if doing so does not negatively affect the timing or performance of the design. If this option is set to 'Always Allow', the Compiler can alter the node or entity, even if doing so affects the timing or performance of the design. Altera does not recommend using this setting. If this option is set to 'Never Allow' the Compiler cannot alter the node or entity.

Type

Enumeration

Values

  • Always Allow
  • Default
  • Never Allow

Device Support

  • Arria 10
  • Arria GX
  • Arria II GX
  • Arria II GZ
  • Arria V
  • Arria V GZ
  • Cyclone
  • Cyclone 10 LP
  • Cyclone II
  • Cyclone III
  • Cyclone III LS
  • Cyclone IV E
  • Cyclone IV GX
  • Cyclone V
  • HardCopy II
  • HardCopy III
  • HardCopy IV
  • MAX 10
  • MAX II
  • MAX V
  • Stratix
  • Stratix GX
  • Stratix II
  • Stratix II GX
  • Stratix III
  • Stratix IV
  • Stratix V

Notes

This assignment supports synthesis wildcards.

Syntax


		set_global_assignment -name ADV_NETLIST_OPT_ALLOWED -entity <entity name> <value>
		set_instance_assignment -name ADV_NETLIST_OPT_ALLOWED -to <to> -entity <entity name> <value>
	

Example


		set_instance_assignment -name adv_netlist_opt_allowed "always allow" -to reg