Altera® Quartus® Prime Standard Edition Settings File Reference Manual

ID 683084
Date 5/08/2017
Public
Document Table of Contents

1.10.87. DUAL_PURPOSE_CLOCK_PIN_DELAY

Specifies the propagation delay from a dual-purpose clock pin to its fan-out destinations that are routed on the global clock network. Legal integer values range from 0 through 63 for Cyclone and Cyclone II device families and from 0 through 11 for Cyclone III, where 0 is the setting with the least delay and 63 is the setting with the most delay. This is an advanced option that should be used only after you have compiled a project, checked the I/O timing, and determined that the timing is unsatisfactory. For detailed information on how to use this option, refer to the data sheet for the device family. This option is ignored if it is applied to anything other than an input or bidirectional pin, or if the pin is user assigned to a non-dual-purpose clock pin location.

Type

Integer

Device Support

  • Cyclone
  • Cyclone 10 LP
  • Cyclone II
  • Cyclone III
  • Cyclone III LS
  • Cyclone IV E
  • Cyclone IV GX
  • MAX 10

Notes

This assignment supports Fitter wildcards.

Syntax


		set_instance_assignment -name DUAL_PURPOSE_CLOCK_PIN_DELAY -to <to> -entity <entity name> <value>