Altera® Quartus® Prime Standard Edition Settings File Reference Manual

ID 683084
Date 5/08/2017
Public
Document Table of Contents

1.7.55. SIGNALRACE_RULE_CLK_PORT_RACE

Direct Design Assistant to check race condition between clock port and any other port of the same register.

Type

Boolean

Device Support

  • Cyclone
  • E
  • MAX II
  • MAX V
  • Mercury
  • Stratix
  • Stratix GX

Notes

None

Syntax


		set_global_assignment -name SIGNALRACE_RULE_CLK_PORT_RACE <value>