Altera® Quartus® Prime Standard Edition Settings File Reference Manual

ID 683084
Date 5/08/2017
Public
Document Table of Contents

1.10.16. AUTO_MERGE_PLLS

Allows the Compiler to automatically find and merge together two compatible phase-locked loops (PLL) driven by the same clock source, reducing the total number of PLLs used in a design.

Type

Boolean

Device Support

  • Arria GX
  • Arria II GX
  • Arria II GZ
  • Cyclone
  • Cyclone 10 LP
  • Cyclone II
  • Cyclone III
  • Cyclone III LS
  • Cyclone IV E
  • Cyclone IV GX
  • HardCopy II
  • HardCopy III
  • HardCopy IV
  • MAX 10
  • Stratix
  • Stratix GX
  • Stratix II
  • Stratix II GX
  • Stratix III
  • Stratix IV

Notes

This assignment supports Fitter wildcards.

This assignment is included in the Fitter report.

Syntax


		set_global_assignment -name AUTO_MERGE_PLLS <value>
		set_global_assignment -name AUTO_MERGE_PLLS -entity <entity name> <value>
		set_instance_assignment -name AUTO_MERGE_PLLS -to <to> -entity <entity name> <value>
	

Default Value

On