Altera® Quartus® Prime Standard Edition Settings File Reference Manual

ID 683084
Date 5/08/2017
Public
Document Table of Contents

1.8.37. EDA_RTL_TEST_BENCH_FILE_NAME

Specifies the RTL simulation test bench file name for Test Bench Mode. File type can be a VHDL Test Bench File (.vht), VHDL File (.vhd), Verilog HDL Test Bench File (.vt), or Verilog HDL file (.v).

Type

File name

Device Support

This setting can be used in projects targeting any Altera device family.

Notes

The value of this assignment is case sensitive.

Syntax


		set_global_assignment -name EDA_RTL_TEST_BENCH_FILE_NAME -section_id <section identifier> <value>
		set_global_assignment -name EDA_RTL_TEST_BENCH_FILE_NAME -entity <entity name> -section_id <section identifier> <value>