Altera® Quartus® Prime Standard Edition Settings File Reference Manual

ID 683084
Date 5/08/2017
Public
Document Table of Contents

1.15.19. VIRTUAL_PIN

Specifies whether an I/O element in a lower-level design entity can be temporarily mapped to a logic element and not to a pin during compilation. The virtual pin is then implemented as a LUT. This option should be specified only for I/O elements that become nodes when imported to the top-level design.

Type

Boolean

Device Support

  • Arria 10
  • Arria GX
  • Arria II GX
  • Arria II GZ
  • Arria V
  • Arria V GZ
  • Cyclone
  • Cyclone 10 LP
  • Cyclone II
  • Cyclone III
  • Cyclone III LS
  • Cyclone IV E
  • Cyclone IV GX
  • Cyclone V
  • HardCopy II
  • HardCopy III
  • HardCopy IV
  • MAX 10
  • MAX II
  • MAX V
  • Mercury
  • Stratix
  • Stratix GX
  • Stratix II
  • Stratix II GX
  • Stratix III
  • Stratix IV
  • Stratix V

Notes

This assignment supports synthesis wildcards.

Syntax


		set_instance_assignment -name VIRTUAL_PIN -to <to> -entity <entity name> <value>