Altera® Quartus® Prime Standard Edition Settings File Reference Manual

ID 683084
Date 5/08/2017
Public
Document Table of Contents

1.14.6. RTLV_SIMPLIFIED_LOGIC

Allow RTL Viewer to remove wire nodes and merge chain of equivalent combinatorial gates

Type

Boolean

Device Support

This setting can be used in projects targeting any Altera device family.

Syntax


		set_global_assignment -name RTLV_SIMPLIFIED_LOGIC <value>
	

Default Value

On