Altera® Quartus® Prime Standard Edition Settings File Reference Manual

ID 683084
Date 5/08/2017
Public
Document Table of Contents

1.10.272. PRESERVE_PLL_COUNTER_ORDER

Preserves the order of PLL clock outputs used when selecting corresponding output counters. For example, a clk0 output will use a C0 counter and a clk2 output will use a C2 counter. Turning this option can cause clock routing problems, as the clock router cannot rotate counters to resolve conflicts.

Type

Boolean

Device Support

  • Arria GX
  • Arria II GX
  • Arria II GZ
  • Cyclone
  • Cyclone 10 LP
  • Cyclone II
  • Cyclone III
  • Cyclone III LS
  • Cyclone IV E
  • Cyclone IV GX
  • HardCopy II
  • HardCopy III
  • HardCopy IV
  • MAX 10
  • Stratix
  • Stratix GX
  • Stratix II
  • Stratix II GX
  • Stratix III
  • Stratix IV

Notes

This assignment supports Fitter wildcards.

Syntax


		set_instance_assignment -name PRESERVE_PLL_COUNTER_ORDER -to <to> -entity <entity name> <value>